The present invention relates generally to a method and apparatus testing logic circuits at the design stage of a semiconductor integrated circuit.
Testing of a semiconductor integrated circuit requires simulation of the logic operations of the logic circuits thereon. As the functional operation of a logic circuit is increased, the number of logic cells which comprise the logic circuit is also increased. The increased number of logic cells leads to an increase in the logic simulation time.
When a logical operation is complicated, as that of a logic circuit which comprises an oscillator element or the like, it is sometimes difficult, if not impossible to adequately model or express on a practically significant scale such a circuit. Even attempts to make the operations as close to physical operations as possible. In such a case, a logic testing apparatus should provide general-purpose functions corresponding to various types of logic circuits to aid the simulation of logic cells.
In designing a semiconductor integrated circuit, its logic circuits are simulated and tested prior to fabrication due to the high cost involved in fabricating such circuits. A testing inspection apparatus of an event-driven type is generally employed for such testing. A set of events is set in such a logic testing apparatus. Each event includes an incoming time, registered on a time axis from the current time of processing to a future time, an incoming place, and a renewed signal value. The logic test apparatus acquires a sub set of events associated with the current time of processing from the set of events and performs an incoming process for each event in the sub set. In the incoming process, the occurrence or generation of a new event is checked and the generated event is registered at the current or future time.
The incoming event generation process is repeated until no event to be processed at the current time is left. When all events are processed, the logic test apparatus renews the current time and repeats the aforementioned incoming process for the time at which the next event is registered.
An incoming process for a logic circuit shown in FIG. 1 will be discussed below. FIG. 2 illustrates the events which are produced in accordance with an incoming process.
When a signal at the output terminal X1 of a first inverter 51 changes to "0" from "1" at time tk0, a first event IV1 whose incoming time is tk0, incoming place is the output terminal X1 and renewed signal value is "0" is registered as shown in FIG. 2.
When the current time reaches time tk0, the logic test apparatus selects the first event IV1 and executes an incoming process for that event IV1. In accordance with the first event IV1, the logic test apparatus sets a signal at the output terminal X1 (incoming place) of the first inverter 51 to "0".
Subsequently, the test apparatus sets the fan-out of the inverter 51 (two in this case), and then sets the value of a signal at a first fan-out pin P1 (signal at the input terminal of a second inverter 52 at the succeeding stage) to "0". Then, based on that signal value, the test apparatus computes the value of a signal at the output terminal X2 of the second inverter 52.
The test apparatus determines if the signal value at the output terminal X2 differs from the signal value at the current time (tk0). In other words, the test apparatus determines that the signal value at the first fan-out pin P1 is "0" and the signal value at the output terminal X2 is "1". When the signal at the output terminal X2 differs from the signal value at the current time, the test apparatus obtains a rise delay time td10 of the second inverter 52 from prestored logic circuit data. Next, the test apparatus generates a second event IV2. As shown in FIG. 2, the second event IV2 has time tk1 after the delay time td10 from the current time tk0 as an incoming time, the output terminal X2 as an incoming place, and a signal value of "1".
When the incoming process for the first fan-out pin P1 is completed, the test apparatus generates an event at a new future time or the current time for a next fan-out pin P2 in a similar manner.
A third inverter 53 has a predetermined rise delay time td20. When a signal at an output terminal X3 is inverted to "1" from "0" as a signal at the fan-out pin P2 of the third inverter 53 changes, the test apparatus generates a third event IV3. As shown in FIG. 2, the third event IV3 has time tk2 after the delay time td20 from the current time tk0 as an incoming time, the output terminal X3 as an incoming place, and a signal value of "1".
When the incoming process for every event at the current time tk0 is completed, the test apparatus updates the current time and executes the above-described incoming process for a time at which a next event is registered.
As discussed above, an event is generated when a signal at the output terminal of one inverter changes. The event used to transfer a change in the signal to the fan-out pin of the inverter.
In such a logic circuit, the terminal structure of a logical model is the same as that of a physical model. In this case, a library representing the logical models of individual cells and a library representing the physical models thereof are stored in a common master library using the concept of sharing cells. The common master library prevents inconsistency between the library of logical models and the library of physical models.
Referring now to FIG. 3, a logic circuit which comprises a fixed-period oscillator element 60 having an odd number of inverters 61 to 65 connected in series is shown. The oscillator element 60 outputs a signal which is an input signal to a first inverter 61. That is, output signal is fed back to the first inverter 61. The signal feedback causes the oscillator element 60 to generate a signal having a predetermined period. An event drive type logic inspection apparatus carries out logic test on such a logic circuit as follows.
When initiating logic testing or at the time of initializing the logic circuit, the test apparatus sets any input signal or output signal of the individual inverters 61-65 which is unsettled or indeterminate to an predetermined unsettled signal value. As a result, the oscillator element 60 is stabilized without oscillating. To make the oscillator element 60 oscillate, therefore, a signal of "1" or "0" for starting oscillation is input to the oscillator element 60. As shown in FIG. 4, the fixed-period oscillator element 60 is provided with a pseudo input terminal 66 for receiving the input signal. At the time of initiating oscillation, a signal of "1" or "0" is externally input to the oscillator element 60 via the pseudo input terminal 66.
Because the pseudo input terminal 66 is needed for logic testing of the oscillator element 60, however, the cell structure of the logical model differs from that of the physical model. The inconsistency between the logical models and the physical models of cells that comprise the oscillator element 60 complicates management of the cell library. In this case, the library of logical models and the library of physical models are managed separately, which undesirably requires inspection and synchronous renewal between the separately managed physical and logical models.
Some semiconductor integrated circuits comprise a variable oscillator element like a PLL (Phase-Locked Loop) element. Testing of such a logic circuit requires logic testing of elements including the PLL element. To accomplish the function of the PLL element, with regard to the oscillation frequency for the voltage of a voltage controlled oscillator (VCO), multiple VCO models may be prepared with multiple oscillation periods according to the resolution of the VCO. Based on a phase difference between a comparison signal and a feedback signal input to the PLL element, the optimal one of the multiple models is properly selected.
FIG. 5 shows an example of the VCO model. In FIG. 5, there are a plurality of fixed-period oscillator elements 60 comprising an odd number of inverters with different oscillation periods. Signals from the individual fixed-period oscillator elements 60 are sent to a selector 67. The selector 67 selects the fixed-period oscillator element 60 which outputs a signal having an oscillation period according to a phase difference between the comparison signal and the feedback signal, and causes that oscillator element 60 to output the signal.
However, this model is not practical because the constituents (VCO models) of the PLL element occupies most of the logic circuit including the PLL element to be tested. Japanese Unexamined Patent Publication No. Hei 9-5397 discloses an apparatus which reduces the number of VCO models as a solution to such a problem. The apparatus is designed based on the fact that the oscillation period of a PLL element and the delay time of the feedback signal to the comparison signal are fixed in accordance with the circuit structure. The apparatus generates a plurality of periods by adjusting the clock input timing based on the results of the previous measurement of the delay of the feedback path. In this case, for logic testing of a logic circuit including a PLL element, the delay of the feedback path is measured every time the circuit is modified.
In view of the above, as shown in FIG. 6, logic test on a PLL element 70 uses a first oscillator 71 whose oscillation period is shifted in the positive direction by time "d" with respect to the target oscillation period of the PLL element 70 and a second oscillator 72 whose oscillation period is shifted in the negative direction by time d. The first oscillator 71 includes a NOR gate 74, an AND gate 75, two inverters 76 and 77 and an AND gate 78. The second oscillator 72 includes the NOR gate 74, the AND gate 75, the two inverters 76 and 77 and an AND gate 79. A phase comparator 73 provides the first oscillator 71 or the second oscillator 72 with a signal S1 according to a phase difference between an external clock REF for the comparison signal and a feedback signal FB. When the external clock REF is delayed from the feedback signal FB, the first oscillator 71 outputs a signal S3 for elongating the oscillation period, in response to the signal S1. When the external clock REF leads to the feedback signal FB, the second oscillator 72 outputs a signal S3 for shortening the oscillation period, in response to the signal S1. The signal from the first oscillator 71 or the second oscillator 72 is input to the phase comparator 73 via a circuit 80 and a frequency divider 81, which are formed on the feedback path. As apparent from the above, the logic test attempts to spontaneously adjust the phase without affecting the delay of the circuit 80.
The delay of the circuit 80, however, keeps oscillation delayed or advanced while the signal S3, indicative of a change in oscillation period, reaches the phase comparator 73 after it is output from the first oscillator 71 or the second oscillator 72. Therefore, the phase adjusting function does not work satisfactorily. Further, the feedback signal FB may be stopped due to a logical error in the circuit 80 in the physical PLL element. In this case, the PLL element 70 determines that the frequency-dividing ratio of a frequency divider 81 is large and gradually shortens the oscillation period. When the comparison signal REF is stopped, on the other hand, the PLL element 70 makes the oscillation period gradually longer.
In the logical model of the PLL element 70 or the model which expresses the PLL element 70 shown in FIG. 6 by the two oscillators 71 and 72, however, the logic circuit keeps operating in the proper period even if the feedback signal FB is stopped, because the periods of the first and second oscillators 71 and 72 are fixed. Thus, a logical error in the circuit 80 may be erroneously overlooked. The PLL element described in the aforementioned Japanese unexamined patent publication also has such a problem.
Further, the oscillation period in the PLL element in either the apparatus described in the aforementioned publication or the logic circuit in FIG. 6 is determined based on the circuit structure. The oscillation period cannot therefore follow up the external clock REF or the switching of the frequency-dividing ratio of the frequency divider 81.
Unlike an element whose operation is logically determined, a PLL element has an analogous property. It is thus difficult to directly adapt no event driven type logic test which can adequately test oscillator circuits. Further, the inclusion of an oscillator in a PLL element makes logic test more difficult.
Accordingly, it is an object of the present invention to provide a logic testing and method, a logic testing apparatus which ensure easier logic testing of a logic cell having an oscillation function.